The invention relates generally to the field of differential amplifiers and operational amplifiers, and more particularly to an integrated circuit amplifier having a rail-to-rail common mode range both at the amplifier inputs and the amplifier output, and still more particularly to such an operational amplifier which is capable of linear, high speed operation with a rail-to-rail supply voltage of as little as approximately 1.2 volts.
The closest prior art includes U.S. Pat. No. 5,311,145 entitled xe2x80x9cCombination Driver-Summing Circuit for Rail-to-Rail Differential Amplifierxe2x80x9d issued May 10, 1994 to Huijsing et al. and incorporated herein by reference, the article xe2x80x9cCompact Low-Voltage Power-Efficient Cells for VLSIxe2x80x9d, by K. Langen and J. Huijsing, IEEE Journal of Solid State Circuits, Volume 33, No. 10, pp. 1482-1496, and the article xe2x80x9cDesign Aspects of Rail-to-Rail CMOS OpAmpxe2x80x9d, by Gierkink, Holzmann, Wiegerink, and Wassenaar, proceedings of the 1st VLSI Workshop, May 6-8, 1997, Columbus, Ohio, pp. 23-28.
FIG. 1 of prior art patent 5,311,145 discloses an operational amplifier capable of xe2x80x9crail-to-rail operationxe2x80x9d. It includes a differential amplifier input stage that includes two pairs of differentially coupled input transistors, one with a tail current to the positive rail and the other with a tail current to the negative rail. A summing circuit is divided into first and second parts biased with a current from a single common floating current source to combine. The drain electrodes of the first pair of input transistors are coupled to the first part, and the drain electrodes of the second par of input transistors are coupled to the second part. A class A-B driver/output stage is coupled to the summing circuit to drive at least one output signal and which is operative over nearly the full rail-to-rail supply voltage range. The article by Langen and Huijsing mainly discloses the circuitry in Patent 5,311,145 in more detail. The paper by Gierkink, Holzmann, Wiegerink, and Wassenaar discloses use of a gain boost amplifier with a cascode connection and a differential amplifier. The circuitry disclosed in this reference is very complex, and needs a large compensation capacitor. There is a need to provide a simpler circuit.
The circuit described in patent 5,311,145 is a two-stage circuit that does not have the capability of operating at a rail-to-rail supply voltage of less than approximately 2.2 volts. Regardless of the power supply voltage, the gain of this circuit is too low for many applications. The speed-power figure of merit for the circuits described in patent 5,311,145 is much lower than desirable at the lower rail-to-rail supply voltage.
All of the known prior art rail-to-rail input/output CMOS operational amplifiers have lower speed than desirable due to parasitic elements in their folded cascode circuits.
Furthermore, noise in the prior art rail-to-rail to input/output CMOS operational amplifiers is higher than desirable because of the presence of the folded cascode transistors in the signal path.
Accordingly, there is an unmet need for a much faster rail-to-rail input/output operational amplifier operable at lower rail-to-rail supply voltages, and with lower noise, than the closest prior art and also operable at a much higher gain-speed-power figure of merit even at the lowest end of the rail-to-rail supply voltage range.
Accordingly, it is an object of the invention to provide an operational amplifier or differential amplifier which is linearly operable at a lower range of rail-to-rail supply voltages than the closest prior art.
It is another object of the invention to provide an operational amplifier or differential and amplifier which is linearly operable lower noise at a lower range of rail-to-rail supply voltage than the closest prior art.
It is another object of the invention to provide a differential amplifier or operational amplifier operable from lower supply voltages and having a substantially higher gain-speed-power figure of merit than the closest prior art, even at lower rail-to-rail supply voltage levels wherein those at which the closest prior art differential or operational amplifiers are operable.
Briefly described, and in accordance with one embodiment thereof, the invention provides a differential amplifier with a rail-to-rail common mode input voltage range, including a first supply voltage rail (V+) and a second supply voltage rail (Vxe2x88x92), first (11) and second (12) input terminals for receiving a differential input signal, and a rail-to-rail input stage, wherein an input signal is applied between gates of differentially connected first (13) and second (14) input transistors of a first channel type, and also is applied between gates of differentially connected third (17) and fourth (18) input transistors of the second channel type. A signal produced by the first input transistor (13) is applied to a junction between a source of a first cascode transistor (26) of the second channel type and a first resistive element (89) also coupled to the first supply voltage rail (V+). A signal produced by the third input transistor (17) is applied to a junction between a source of a second cascode transistor (37) of the first channel type and a second resistive element (88) also coupled to the second supply voltage rail (Vxe2x88x92). A signal produced between a drain of the first input transistor (13) and a drain of the second input transistor (14) is applied between first (xe2x88x92) and second (+) inputs of a first gain boost amplifier (58A) having an output (64) coupled to the gate of the first cascode transistor (26). A signal produced between the drain of the third input transistor (17) and the drain of the fourth input transistor (18) is applied between first (xe2x88x92) and second (+) inputs of a second gain boost amplifier (57A) having an output (56) coupled to the gate of the second cascode transistor (37). An output stage includes a pull-up transistor (30) of the second channel type coupled between the first supply voltage rail and the output terminal, a pull-down transistor (45) of the first channel type coupled between the second supply voltage rail (Vxe2x88x92) and the output terminal, and a class AB bias circuit (29) coupled between drain electrodes of the first (26) and second (37) cascode transistors, which are coupled to gate electrodes of the pull-up and pull-down transistors, respectively.
A first amplification path through the source of the first cascode transistor (26) constitutes a high frequency signal amplification path, and a second amplification path through the gate of the first cascode MOSFET (26) constitutes a lower frequency amplification path in parallel with the first amplification path. A third amplification path through the source of the second cascode transistor (37) constitutes a high frequency signal amplification path, and a fourth amplification path through the gate of the second cascode MOSFET (37) constitutes a lower frequency amplification path in parallel with the third amplification path. In the described embodiments, a bias transistor (85) is coupled between the second input (+) of the first gain boost amplifier (58A) and the second input (+) of the second gain boost amplifier (57A). The gate of the bias transistor (85) is connected to a gate of a feedback reference transistor (83) and to an output (84) of a control amplifier (80). A first input (+) of the control amplifier (80) is coupled to a junction (82) between a source of the feedback reference transistor (83) and a constant current source (81), and a second input (xe2x88x92) of the control amplifier (80) is coupled to the source of the bias transistor (85).